is reportedly considering a price increase of up to 20 percent for its CoWoS advanced packaging technology. This potential hike is driven by surging demand for and custom , which has significantly strained the company's current supply.
Manufacturing difficulty is rising as more compute dies and stacks are integrated into single packages. Larger chip sizes reduce equipment output while testing times lengthen. New facilities take three years to reach full load as lead times increase.
TSMC targets a capacity of 130,000 monthly wafers by 2026 and 200,000 units by 2027, with a U.S. plant opening in 2028. The firm is also developing 9x and 14x reticle-size packages and panel-based CoPoS technology to meet future high-performance demands.