Chinese memory firm has begun production of memory chips, utilizing a process that stacks eight DRAM layers connected by through silicon vias. These modules feature 3,000 TSV cutouts and a base die to facilitate communication with computer systems.
Current reports indicate CXMT faces significant manufacturing hurdles, with HBM3 yields between 25% and 30%. Approximately 80 out of 100 chips fail initial quality clearance, though 70% of final products pass subsequent testing for domestic DRAM supply chains.
CXMT enters a competitive market led by SK hynix, Micron, and Samsung. While rivals explore hybrid bonding for HBM4 to replace bumps with underfill, CXMT focuses on scaling its current 8-layer HBM3 output to support the growing Chinese technology sector.